REINFORCEMENT LEARNING BASED FLOORPLANNING STRATEGY FOR AREA AND WIRELENGTH OPTIMIZATION IN LARGE SCALE VLSI ARCHITECTURES
Keywords:
Reinforcement Learning (RL), VLSI Floorplanning, Area Optimization, Wirelength Minimization, Markov Decision Process (MDP), Neural Policy Approximation, Large Scale Integration, Physical Design AutomationSynopsis
Floorplanning is a a pivotal phase in Very Large-Scale Integration (VLSI) design that significantly impacts performance, cost, manufacturability, and power efficiency. Traditional optimization methods such as Simulated Annealing, Genetic Algorithms, and analytical approaches perform adequately but face scalability challenges in large-scale designs with millions of netlists.
This work proposes an end-to-end Reinforcement Learning (RL)-based floorplanning framework tailored for large VLSI architectures. The problem is formulated as a Markov Decision Process (MDP), where an RL agent sequentially places macros and standard cells to jointly optimize area utilization and wirelength under design constraints.
A deep neural network encodes placement states and learns an optimal policy through reward functions balancing area efficiency and interconnection minimization. Experimental results on benchmark circuits show up to 18% area reduction and 24% wirelength improvement compared to heuristic baselines.
The proposed approach demonstrates the potential of learning-based optimization for physical design, enabling scalable and adaptive solutions within modern Electronic Design Automation (EDA) workflows.
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